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W946432AD 512K x 4 BANKS x 32 BITS DDR SDRAM
GENERAL DESCRIPTION
The W946432AD is a high-speed CMOS Double Data Rate synchronous dynamic random access memory organized as 512K words x 4 banks x 32 bits. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The W946432AD operates from a differential clock (CLK and CLK the crossing of CLK going HIGH and CLK going LOW will be referred to as the postive edge of CLK). Commands (address and control signals) are registered at every positive edge of CLK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CLK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4 or 8 locations. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.
FEATURES
*Double-data-rate
architecture; two data transfers
*Four *Data *Burst *CAS
internal banks for concurrent operation mask (DM) for write data lengths: 2, 4, or 8 Latency: 3
per clock cycle
*Bidirectional,
data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver is edge-aligned with data for READs; center-aligned with data for WRITEs clock inputs (CLK and CLK )
*DQS
*AUTO *Auto
PRECHARGE option for each burst access Refresh and Self Refresh Modes Maximum Average Periodic Refresh Interval (SSTL_2 compatible) I/O = 2.5V 0.2V = 2.5V 0.2V
*Differential *DLL
aligns DQ and DQS transitions with CLK transitions DLL on or DLL off mode
*15.6us *2.5V
*Programmable *
Commands entered on each positive CLK edge; data and data mask referenced to both edges of DQS
*VDDQ *VDD
PRELIMINARY DATA:9/8/00 1
W946432AD 512K x 4 BANKS x 32 BITS DDR SDRAM
PIN CONFIGURATION
VDDQ
VDDQ
DQ31
DQ30
DQ29
VSSQ
VSSQ
VSSQ
DQS
DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DM0 DM2 WE CAS RAS CS BA0 BA1
1 2 3 4 5 6 7 8 9
100 99 98 97 96 95 94 93 92
DQ2 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A0
31 32 33 34 35 36 37 38 39
DQ1 A2
DQ0
VDD
VSS
N.C
91 90 89 88 87 86 85 84 83 82 81
40 41 42 43 44 45 46 47 48 49 50
N.C
N.C
N.C
N.C
N.C
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ VREF DM3 DM1 CLK CLK CKE N.C A8/AP
A1
A3
VDD
A10
N.C
N.C
N.C
N.C
N.C
N.C
N.C
2
N.C
A9
VSS
A4
A5
A6
A7
PRELIMINARY DATA:9/8/00
W946432AD
PIN DESCRIPTION
PIN NAME FUNCTION DESCRIPTION All address and control input signals are sampled on the crossing of the positive edge of CLK CLK, CLK Differential clock input and negative edge of CLK . Output (read) data is referenced to the crossings of CLK and CLK (both directions of crossing).
CKE
Clock Enable
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CLK, CLK and CKE are disabled during POWER-DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH.
CS
Chip Select
All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code.
RAS , CAS , WE
Command Inputs
RAS , CAS and WE (along with CS ) define the command being entered. DM is an input mask signal for writes data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A8 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the opcode during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).
DM
Input Data Mask
BA0, BA1
Bank Address
A0-A10
Address Input
DQ DQS VDDQ VSSQ VDD VSS NC VREF
Data Input/Output Data bus Data Strobe DQ Power DQ Ground Supply Power No Connection Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. 2.5V 0.2V. Ground. 2.5V 0.2V Ground. No connection SSTL_2 reference voltage.
W946432AD
BLOCK DIAGRAM
CLK CLK
DLL CLOCK BUFFER
CKE
CONTROL
CS
SIGNAL
RAS CAS
GENERATOR COMMAND
DECODER
WE
COLUMN DECODER
COLUMN DECODER
ROW DECODER
A8
CELL ARRAY BANK #0
ROW DECODER
CELL ARRAY BANK #1
A0 A7, A9,A10 BA0 BA1
ADDRESS BUFFER
MODE REGISTER SENSE AMPLIFIER
SENSE AMPLIFIER
Prefetch Register DATA CONTROL CIRCUIT REFRESH COUNTER COLUMN COUNTER DQ BUFFER
DQ0 DQn DQS DM
COLUMN DECODER
COLUMN DECODER
ROW DECODER
CELL ARRAY BANK #2
ROW DECODER
CELL ARRAY BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE: The cell array configuration is 2048 * 256 * 32
W946432AD
ABSOLUTE MAXIMUM RATINGS*
SYMBOL VIN VOUT VDD VDDQ TOPR TSTG TSOLDER PD IOUT Input Voltage Output Voltage Power Supply Voltage I/O Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature(10s) Power Dissipation Short Circuit Output Current ITEM RATING -0.3~ VDD +0.3 -0.3~ VDDQ+0.3 -0.3~4.6 -0.3~3.6 0~70 -55~150 260 1 50 UNIT V V V V C C C W mA NOTES 1 1 1 1 1 1 1 1 1
*Conditions outside the limits listed under "Absolute Maxi-mum Ratings" may cause permanent damage to the device.
CAPACITANCE (VDDQ = 2.5V, VDD = 2.5 0.2, f 100 MHz, TA = 25 C)
PARMETER Input Capacitance: CK, CK Input Capacitance: All other input-only pins Input/Output Capacitance: DQ, DQS, DM Note: These parameters are periodically sampled and not 100% tested. SYMBOL Cl1 Cl2 Cl0 MIN 2.5 2.5 4.0 MAX 3.5 3.5 5.5 UNITS pF pF pF NOTES
ELECTRICAL CHARACTERISTICS AND DC OPERATING CONDITIONS (0C TA 70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V)
PARAMETER/CONDITION Supply Voltage (for devices with VDD of 2.5V) I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs INPUT LEAKAGE CURRENT SYMBOL VDD VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) II MIN 2.3 2.3 1.15 VREF -0.04 VREF +0.18 -0.3 -0.3 0.36 -5 MAX 2.7 2.7 1.35 VREF + 0.04 VDD + 0.3 VREF -0.18 VDDQ + 0.3 VDDQ + 0.6 5 UNITS V V V V V V V V
uA
NOTES
3 4
5
Any input 0V VIN VDD (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V VOUT VDDQ) OUTPUT LEVELS Output High Current (VOUT = 1.95V) Output Low Current (VOUT = 0.35V)
IOZ IOH IOL
-5 -15.2 15.2
5
uA
mA mA
W946432AD
AC OPERATING CONDITIONS (0C TA 70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V)
PARAMETER/CONDITION Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs SYMBOL VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 MIN VREF + 0.35 VREF 0.35 VDDQ + 0.6 0.5*VDDQ+0.2 MAX UNITS V V V V 5 7 NOTES
IDD SPECIFICATIONS AND CONDITIONS (0C TA 70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V)
MAX SYMBOL OPERATING CURRENT: One Bank; Active-Precharge; tRC = tRC MIN; tCK = tCK MIN; DQ, DM and DQS inputs changing twice per clock cyle; address and control inputs changing once per clock cycle OPERATING CURRENT: One Bank; Active-Read-Precharge; Burst = 2; tRC = tRC MIN; CL = 3 ; tCK = tCK MIN; IOUT= 0 mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; power-down mode; CKE IDD0 TBD UNITS mA NOTES
IDD1
TBD
mA
IDD2P IDD2N
TBD TBD
mA mA
VIL (MAX); tCK = tCK MIN
CKE VIH (MIN); tCK = tCK MIN; Address and other control inputs changing once per clock cycle ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; power-down mode; CKE
IDLE STANDBY CURRENT: CS
VIH (MIN); All banks idle;
IDD3P IDD3N
TBD TBD
mA mA
VIL (MAX); tCK = tCK MIN
ACTIVE STANDBY CURRENT: CS VIH (MIN); CKE VIH (MIN); One bank; Active-Precharge; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM and DQS inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; CL = 3 ; tCK = tCK MIN; IOUT = 0 mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; CL = 3 ; tCK = tCK MIN; DQ, DM and DQS inputs changing twice per clock cycle AUTO REFRESH CURRENT: tRC = tRFC (MIN) SELF REFRESH CURRENT: CKE
IDD4R
TBD
mA
IDD4W
TBD
mA
IDD5 IDD6
TBD TBD
mA mA
0.2V
W946432AD 512K x 4 BANKS x 32 BITS DDR SDRAM
AC CHARACTERISTICS
(0C TA 70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V) PARAMETER
DQ output access time from CLK/ CLK DQS output access time from CLK/ CLK CLK high-level width CLK low-level width Clock cycle time DQ and DM input hold time DQ and DM input setup time DQ and DM input pulse width (for each input) Data-out high-impedance time from CLK/ CLK Data-out low-impedance time from CLK/ CLK DQS-DQ Skew (for DQS and associated DQ signals) DQS-DQ Skew (for DQS and all DQ signals) DQ/DQS output valid time Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width DQS falling edge to CLK setup time DQS falling edge hold time from CLK MODE REGISTER SET command cycle time Write postamble Write preamble Address and Control input hold time Address and Control input setup time Read preamble Read postamble ACTIVE to PRECHARGE command ACTIVE to ACTIVE/Auto Refresh command period Auto Refresh to Active/Auto Refresh command period ACTIVE to READ or WRITE delay PRECHARGE command period ACTIVE bank A to ACTIVE bank B command Write recovery time Auto Precharge write recovery + precharge time Internal Write to Read Command Delay Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command Average Periodic Refresh Interval tAC tDQSCK tCH tCL tCLK tDH tDS tDIPW tHZ tLZ tDQSQ tDQSQA tDV tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE TIH TIS tRPRE tRPST tRAS tRC tRFC tRCD tRP tRRD tWR tDAL tWTR tXSNR tXSRD tREFI
-4 -5 -6 UNIT MIN. MAX. MIN. MAX. MIN. MAX.
-0.1 -0.1 0.45 0.45 4 0.5 0.5 1 -0.1 -0.1 -0.5 -0.5 0.35 0.75 0.35 0.35 0.2 0.2 2 0.4 0.25 1 1 0.9 0.4 35 47 47 3 3 2 2 5 2 47 200 15.6 0.1 0.1 0.55 0.55 8 -0.1 -0.1 0.45 0.45 5 0.5 0.5 1.6 0.1 0.1 0.55 0.55 8 -0.1 -0.1 0.45 0.45 6 0.5 0.5 1.6 0.1 0.1 0.55 0.55 8 tCK tCK tCK tCK ns ns ns ns tCK tCK -0.5 0.35 0.75 0.4 0.4 0.5 -0.5 0.35 0.75 0.4 0.4 0.5 ns ns tCK tCK tCK tCK tCK tCK tCK tCK tCK ns ns tCK tCK ns ns ns tCK tCK tCK tCK tCK tCK ns tCK us
NOTE
8
0.1 0.1 0.5 0.5 1.25 1.25 0.6 0.6 1.25 0.6 0.6
0.6
1.1 0.6
0.9 35 55 66 15 15 11 10 25
1.1 120K
0.9 42 60 72 18 18 12 12 30
1.1 120K
9
200 15.6
200 15.6
PRELIMINARY DATA:9/8/00 7
W946432AD 512K x 4 BANKS x 32 BITS DDR SDRAM
NOTES 1. All voltages referenced to VSS. 2. Outputs measured with equivalent load:
VTT
RT = 25 ohms
Rs = 25 ohms 30pF
A.C TEST LOAD
3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-2% of the DC value. 4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 5. VID is the magnitude of the difference between the input level on CK and the input level on CK . 6. IDD specifications are tested after the device is properly initialized. 7. VIX is the differential clock cross point voltage where input timing measurement is referenced.
CLK Vix CLK VssQ Vix
8. Beyond 8ns tCK, chip maybe in "DLL off" mode 9. WRITE interrupted by READ is not allowed.
Note:
PRELIMINARY DATA:9/8/00 8
W946432AD
FUNCTIONAL DESCRIPTION
The W946432AD is a high speed CMOS, dynamic random access memory containing 67,108,864 bits. The W946432AD is internally configured as a quad bank DRAM. The W946432AD uses a double data rate architecture to achieve high speed operation. The double data rate architecture is essentially a 32 prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the W946432AD consists of a single 32bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding 32bit wide, one half clock cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A10 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide etailed information covering device initialization, register definition, command descriptions and device operation.
INITIALIZATION
W986432AD must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch up, which may cause permanent damage to the device. VREF can be applied any time after VDDQ, but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power up is required to guarantee that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200s delay prior to applying an executable command. Once the 200s delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and any read command. A PRECHARGE ALL command should be applied, placing the device in the "all banks idle" state. Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.
9
W946432AD
REGISTER DEFINITION
MODE REGISTER The Mode Register is programmed by the MODE REGISTER SET command (MRS/EMRS) when all banks are idle and no bursts are in progress. The Mode Register is used to define the operation specific mode of of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure1: The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functionsinclude DLL enable/disable,output drive strength selection. These functions as shown inFigure1:. Mode Register must be loaded, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Figure1:Mode Register Definition
MODE REGISTER DEFINITION
BA0 BA1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
EXTENDED MODE REGISTER DEFINITION
BA0 BA1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 0*
12 0*
10
9
8
7
6
5
4 BT
3
2
1
0
Extended Mode Register
12 1*
11 0*
10
9
8
7
6
5
4
3
2
1
0
Extended Mode Register
Operating Mode
CAS Latency
Burst Latency
Operating Mode
DS2 DS1 DS0 DLL
* BA0 and BA1 must be 0, 0 to select the Mode Register (vs. the Extended Mode Register).
Burst Latency A2 A1 A0 000 001 010 011 100 101 110 111 A3 = 0 Reserved 2 4 8 Reserved Reserved Reserved Reserved A3 = 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved
* BA0 and BA1 must be 1, 0 to select the Extended Mode Register (vs. the base Mode Register).
A0 0 1
DLL Enable Disable
A1 0 1
DS0 Normal Weak (optional)
A3 0 1
Burst Type Sequential Interleaved
A2 0 1
DS1
A6 A5 A4 000 001 010 011 100 101 110 111
CAS Latency Reserved Reserved Reserved 3 Reserved Reserved Reserved Reserved
A3 0 1
DS2
A10-A4 0
A3-A0 Valid -
Operating Mode Normal Operation All other states reserved
An-A9 0 0 0 -
A8 A7 0 1 0 0 0 1 -
A6-A0 Valid Valid VS -
Operating Mode Normal Operation Normal Operation/Reset DLL Vendor Specific Test Mode All other states reserved
-
VS = Vendor Specific
10
W946432AD
Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Table 1: The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place with in this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when the burst length is set to two, by A2-A7 when the burst length is set to four and by A3-A7 when the burst length is set to eight. The remaining address bit is used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected by bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1:. Table 1:BURST DEFINITION
Burst Length 2 A1 0 0 1 1 A1 0 0 1 1 0 0 1 1 Starting Column Address: A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
4
8
A2 0 0 0 0 1 1 1 1
NOTE: 1. For a burst length of two, A1-A7 selects the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-A7 selects the four-data-element block; A0-A1 selects the first access within the block. 3. For a burst length of eight, A3-A7 selects the eight-data- element block; A0-A2 selects the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
11
W946432AD
Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency is set to 3 clocks. If a READ command is registered at clock edge n, and the latency is 3 clocks, the data will be available nominally coincident with clock edge n + 3. Figure2:REQUIRED CAS LATENCIES
REQUIRED CAS LATENCIES CK CK COMMAND READ NOP CL=3 DQS NOP NOP NOP NOP
DQ DON'T CARE
Burst Length = 4 in the case shown Shown with nominal tAC, tDQSCK, and tDQSQ
Operating Mode The normal operating mode is selected by issuing a Mode Register Set command with bits A7-A10 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is inititated by issuing a Mode Register Set command with bits A7 and A9-A10 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode. All other combinations of values for A7-A10 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable isrequiredduringpower-upinitialization,andupon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Output Drive Strength DS0, DS1, DS2, TBD
12
W946432AD
COMMANDS
Truth Table provides a quick reference of available commands. This is followed by a verbal description of each command. The additional Function Truth Tables provide current state/ next state information. TRUTH TABLE (NOTE 1, 2)
Symbol Command Device State Idle (3) Any (3) Any Active (3) Active (3) Active (3) Active (3) Idle Any Active (4) Any Idle Idle Idle (S.R) Idle Active (5) Any (Power down) Active Active CKEn-1 CKEn H H H H H H H H H H H H H H L H L H H X X X X X X X X X X X X H L H L H X X DM X X X X X X X X X X X X X X X X X L H BA0,1 V V X V V V V L,L H,L X X X X X X X X X X A8 V L H L H L H V V X X X X X X X X X X A10, A9-0 V X X V V V V V V X X X X X X X X X X
CS
L L L L L L L L L L L H L L H L H L H L X X
RAS CAS
L L L H H H H L L H H X L L X H X H X H X X H H H L L L L L L H H X L L X H X H X H X X
WE H L L L L H H L L H L X H H X X X X X X X X
ACT PRE PREA WRIT WRITA READ READA MRS EMRS NOP BST DSL AREF SELF SELEX PD PDEX WDE WDD
Bank Active Bank Precharge Precharge All Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Set Extended Mode Register Set No-Operation Burst Read Stop Device Deselect Auto-Refresh Self-Refresh Entry Self-Refresh Exit Power Down Mode Entry Power Down Mode Exit Data Write Enable Data Write Disable
Notes: (1) V = Valid, X = Don't care, L = Low Level, H = High Level (2) CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the command provided. (3) These are state of bank designated by BA0 BA1 signals. (4) Applies only to read bursts with autoprecharge disabled; this command should not be used for read bursts with autoprecharge enabled, and for write bursts. (5) Power Down Mode can not be entered in the burst cycle.
13
W946432AD
Function TRUTH TABLE (NOTE 1)
CURRENT STATE CS H L L L L L L L H L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L RAS X H H H L L L L X H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L CAS X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L WE X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L Address X X BA, CA,A8 BA, CA,A8 BA, RA BA, A8 X Op-Code X X BA, CA,A8 BA, CA,A8 BA, RA BA, A8 X Op-Code X X X BA, CA,A8 BA, CA,A8 BA, RA BA, A8 X Op-Code X X X BA, CA,A8 BA, CA,A8 BA, RA BA, A8 X Op-Code X X X BA, CA,A8 BA, CA,A8 BA, RA BA, A8 X Op-Code X X X BA, CA,A8 BA, CA,A8 BA, RA BA, A8 X Op-Code Command DSL NOP, BST Read, Read A Write, Write A ACT PRE, PRE A AREF, SREF MRS, EMRS DSL NOP, BST Read, Read A Write, Write A ACT PRE, PRE A AREF, SREF MRS, EMRS DSL NOP BST Read, Read A Write, Write A ACT PRE, PRE A AREF, SREF MRS, EMRS DSL NOP BST Read, Read A Write, Write A ACT PRE, PRE A AREF, SREF MRS, EMRS DSL NOP BST Read, Read A Write, Write A ACT PRE, PRE A AREF, SREF MRS, EMRS DSL NOP BST Read, Read A Write, Write A ACT PRE, PRE A AREF, SREF MRS, EMRS ACTION NOP NOP ILLEGAL ILLEGAL ACTIVE (select and activate row) NOP Refresh or Self refresh Mode register accessing NOP NOP READ (start READ burst) WRITE (start WRITE burst) ILLEGAL PRECHARGE ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop Term burst, start new READ burst ILLEGAL ILLEGAL Term burst, PRECHARGE ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL Term burst, start new READ burst ILLEGAL Term burst, PRECHARGE ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOTE
Idle
3 3
2 2
Row Active
4 4 3 5
6 3
Read
Write
3 6,7 3 8
Read with Auto rpecharge
Write with Auto precharge
14
W946432AD
NOTE:
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH. 2. ILLEGAL if any bank is not idle. 3. ILLEGAL to bank in specified states; Function may be legal in the bank indicated by Bank Address(BA), depending on the state of that bank. 4. ILLEGAL if tRCD is not satisfied. 5. ILLEGAL if tRAS is not satisfied. 6. Must satisfy bust interrupt condition. 7. Must satisfy bus contention, bus turn around, and/ or write recovery requirements 8. Must mask preceding data, which don't satisfy tWR
Figure3:Simplified State Diagram
SIMPLIFIED STATE DIAGRAM
SELF REFRESH
SREF SREFX
IDLE
MRS/EMRS
MODE REGISTER SET
AREF
AUTO REFRESH
PD
PDEX ACT
ACTIVE POWERDOWN POWER DOWN
PDEX PD
ROW ACTIVE
BST Read Read
Write
Write
Write
Read
Read A Write A Write A Read A
PRE
Write A
PRE
PRE
Read A
POWER APPLIED
POWER ON
PRE
PRE CHARGE
Automatic Sequence Command Sequence
MRS = Mode Register Set EMRS = Extended Mode Register Set SREF = Enter Self Refresh SREFX = Exit Self Refresh AREF = Auto Refresh PD = Enter Power Down PDEX = Exit Power Down
ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge BST = B nst Read Stpop
15
W946432AD
DESELECT The Device Deselect command disables the command decoder so that the RAS CAS WE and Address inputs are ignored. This command is similar to the No-Operation command. NO OPERATION (NOP) The No Operation Command should be used in cases when the DDR SDRAM is in an idle or a wait state to prevent the DDR SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS , CAS , and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. MODE REGISTER SET Command is registered when CS , RAS , CAS , and WE is at the rising edge of the clock. The mode registers are loaded by inputs A0-A10. See mode register descriptions in the Register Definition section. The MODE REGISTER SET command can only be issued when all banks are idle and no bursts are in progress, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is registered when CS , RAS is low with CAS , and WE held high at the rising edge of the clock, used to open a row in a particular bank for a subsequent access. READ The READ command is registered when CS , CAS is low with RAS , and WE held high at the rising edge of the clock, used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A7 selects the starting column location. WRITE The WRITE command is registered when CS , CAS , WE is low with RAS , held high at the rising edge of the clock, used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A7 selects the starting column location PRECHARGE The PRECHARGE command is registered when CS , RAS , WE is low with CAS held high at the rising edge of the clock, used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time ( tRP) after the PRECHARGE command is issued. Input A8 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank. BURST READ STOP The BURST READ STOP command register when CS WE is low with RAS CAS held high is used to truncate read bursts (with autoprecharge disabled). AUTO REFRESH The Auto Refresh command is register when CS RAS CAS low with WE high. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. The W946432AD requires AUTO REFRESH cycles at an average periodic interval of 15.6s (maximum). 16
W946432AD
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 9 * 15.6us (140.4us). This maximum absolute interval is short enough to allow for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing too much drift in tAC between updates. SELF REFRESH The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH, and is automatically enabled upon exiting SELF REFRESH (200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are "Don't Care" during SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.
OPERATIONS
BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank must be "opened." This is accomplished by the ACTIVE command, which selects both the bank and the row to be activated. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A10 selects the row. The maximum time that each bank can be held in the active state is specified as tRAS (max). After this command is issued, Read or Write operation can be executed. After opening a row, a READ or WRITE command may be issued to that row, subject to the tRCD specification. A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
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PRELIMINARY DATE: 9/8/00 .
W946432AD
Figure4:tRCD and tRRD Definition
tRCD and tRRD Definition CK CK COMMAND ACT NOP NOP ACT NOP NOP RD/WR NOP
A0-A10
Row
Row
Col
BA0,BA1
Bank x tRRD
Bank y tRCD
Bank y
DON'T CARE
READs The starting column and bank addresses are provided with the READ command and AUTO PRECHARGE is either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled (A8 = high), the row that is accessed will start precharge at the completion of the burst. This command cannot be interrupted by any other command. For the generic READ commands used in the following illustrations, AUTO PRECHARGE is disabled (A8 = low). During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge. Figure5: shows general timing. DQS is driven by the DDR SDRAM along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coincident with the last data-out element is known as the read post amble. Upon completion of a burst, assuming no other commands have been initiated, the DQS will go High-Z. Data from any READ burst may be concatenated with or truncated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles after the first READ command, where x equals the number of desired data element pairs (pairs are required by the 32 prefects architecture). This is shown in Figure6:. A READ command can be initiated on any clock cycle following a previous READ command. Non-consecutive READ data is shown for illustration in Figure7:. Full-speed random read accesses within a page (or pages) can be performed as shown in Figure8:. Data from any READ burst may be truncated with a BURST READ STOP command, as shown in Figure9:The BURST READ STOP latency is equal to the read ( CAS ) latency. Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST READ STOP command must be used, as shown in Figure10:. A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that AUTO PRECHARGE was not activated). The PRECHARGE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs. Note that part of the row precharge time is hidden during the access of the last data elements.
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PRELIMINARY DATE: 9/8/00 .
W946432AD
In the case of a READ being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same READ burst with AUTO PRECHARGE enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate bursts. Figure5:READ BURST - REQUIRED CAS LATENCIES
READ BURST - REQUIRED CAS LATENCIES CK CK COMMAND READ Bank, Col n CL=3 DQS NOP NOP NOP NOP NOP
ADDRESS
DQ
DO n DON'T CARE
DO n = Data Out from column n Burst Length = 4 Show with nominal tAC, tDQSCK, and tDQSQ
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PRELIMINARY DATE: 9/8/00 .
W946432AD
Figure6:CONSECUTIVE READ BURSTS - REQUIRED CAS LATENCIES
CONSECUTIVE READ BURSTS - REQUIRED CAS LATENCIES CK CK COMMAND READ Bank, Col n CL=3 DQS DO n DO b DON'T CARE
DO n (or b) = Data Out from column n (or column b) Burst Length = 4 Shown with nominal tAC, tDQSCK, and tDQSQ Read commands shown must be to the same device
NOP
READ Bank, Col n
NOP
NOP
NOP
NOP
ADDRESS
DQ
Figure7:NON - CONSECUTIVE READ BURSTS - REQUIRED CAS LATENCIES
NON CONSECUTIVE READ BURSTS - REQUIRED CAS LATENCIES CK CK COMMAND READ Bank, Col n CL=3 DQS DO b DON'T CARE
DO n (or b) = Data Out from column n (or column b) Burst Length = 4 Shown with nominal tAC, tDQSCK, and tDQSQ
NOP
NOP
READ Bank, Col b
NOP
NOP
NOP
ADDRESS
DQ
DO n
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PRELIMINARY DATE: 9/8/00 .
W946432AD
Figure8:RANDOM READ ACCESSES - REQUIRED CAS LATENCIES
RANDOM READ ACCESSES - REQUIRED CAS LATENCIES CK CK COMMAND READ Bank, Col n READ Bank, Col x CL=3 READ Bank, Col b READ Bank, Col g READ NOP NOP
ADDRESS
DQS DO n DO n' DO x DO x' DO b DO b' DO g
DQ
DON'T CARE
DO n, etc. = Data Out from column n, etc. n', etc. = the next Data Out following DO n, etc. according to the programmed burst order Burst Length = 4 Reads are to active rows in any banks Shown with nominal tAC, tDQSCK, and tDQSQ
Figure9:BURST READ STOP- REQUIRED CAS LATENCIES
TERMINATING A READ BURST - REQUIRED CAS LATENCIES CK CK COMMAND READ Bank, Col n CL=3 DQS NOP BST NOP NOP NOP
ADDRESS
DQ
DO n DON'T CARE
DO n = Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements Shown with nominal tAC, tDQSCK, and tDQSQ
21
W946432AD
Figure10:READ TO WRITE - REQUIRED CAS LATENCIES
READ TO WRITE - REQUIRED CAS LATENCIES CK CK COMMAND READ Bank, Col n CL=3 DQS BST NOP NOP NOP WRITE Bank, Col b NOP
ADDRESS
tDQSS
DQ DM
DO n
DON'T CARE
DO n (or b) = Data Out from column n (or column b) Burst Length = 4 Data In elements are applied following DI b in the programmed order Shown with nominal tAC, tDQSCK, and tDQSQ
Figure11:READ TO PRECHARGE - REQUIRED CAS LATENCIES
READ TO PRECHARGE - REQUIRED CAS LATENCIES CK CK COMMAND READ Bank, Col n CL=3 DQS DO n DON'T CARE
DO n (or b) = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 Shown with nominal tAC, tDQSCK, and tDQSQ
NOP
PRE Bank (a or all)
NOP
NOP
ACT Bank, Row
tRP
ADDRESS
DQ
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W946432AD
WRITEs The starting column and bank addresses are provided with the WRITE command, and AUTO PRECHARGE is either enabled or disabled for that access. If AUTO PRECHARGE is enabled (A8=HIGH), the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is disabled (A8=LOW), the row will remain open for subsequent accesses. During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the write command, and subsequent data elements will be registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write post amble. The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75% to 125% of 1 clock cycle), Figure12: show the two extremes of tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQS will remain High-Z and any additional input data will be ignored. Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on any positive edge of clock following the previous WRITE command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst, which is being truncated. The new WRITE command should be issued x cycles after the first WRITE command, where x equals the number of desired data element pairs Figure13: show concatenated bursts of 4. An example of non-consecutive WRITEs is shown in. 0 Full-speed random write accesses within a page or pages can be performed as shown in. Figure15: Data for any WRITE burst may be followed by a subsequent READ command. To follow a WRITE without truncating the write burst, tWTR should be met as shown in Figure16:. Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating the write burst, tWR should be met as shown in 0. Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as shown in Figure18: Figure19:. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data-in should be masked with DM, as shown in Figure18: Figure19:. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until t RP is met. POWER-DOWN Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE. For maximum power savings, the user has the option of disabling the DLL prior to entering power-down. In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur before a READ command can be issued. However, power-down duration is limited by the refresh requirements of the device, so in most applications, the selfrefresh mode is preferred over the DLL-disabled power-down mode. In power-down, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR SDRAM, and all other input signals are "Don't Care". The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT command). A valid executable command may be applied one clock cycle later.
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W946432AD
Figure12:WRITE BURST - DQSS
T0 CK CK COMMAND WRITE Bank, Col b NOP NOP NOP WRITE BURST - DQSS T1 T2 T3 T4 T5 T6 T7
ADDRESS
tDQSS
DQS DI b
DQ
DM DON'T CARE
DI b, etc. = Data In for column b, etc. A non-interrupted burst of 4 is shown A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
Figure13:WRITE TO WRITE - DQSS
T0 CK CK COMMAND WRITE Bank, Col b NOP WRITE Bank, Col n NOP NOP NOP T1 WRITE TO WRITE - DQSS T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
ADDRESS
tDQSS
DQS DI b DI n
DQ
DM DON'T CARE
DI b, etc. = Data In for column b, etc. A non-interrupted burst of 4 is shown
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PRELIMINARY DATE: 9/8/00 .
W946432AD
Figure14:WRITE TO WRITE DQSS, NON - CONSECUTIVE
T0 CK CK COMMAND WRITE Bank, Col b NOP NOP WRITE Bank, Col n NOP WRITE TO WRITE DQSS, NON - CONSECUTIVE T1 T2 T3 T4 T5 T6 T7 T8 T9
ADDRESS
tDQSS
DQS DI b DI n
DQ
DM DON'T CARE
DI b, etc. = Data In for column b, etc. A non-interrupted burst of 4 is shown Each Write command may be to any bank, and may be to the same or different devices Depending on external components
Figure15:RANDOM WRITE CYCLES - DQSS
T0 CK CK COMMAND WRITE Bank, Col b WRITE Bank, Col x WRITE Bank, Col n WRITE Bank, Col a WRITE Bank, Col g T1 RANDOM WRITE CYCLES - DQSS T2 T3 T4 T5 T6 T7 T8 T9
ADDRESS
tDQSS
DQS DI b DI b' DI x DI x' DI n DI n' DI a DI a'
DQ
DM DON'T CARE
DI b, etc. = Data In for column b, etc. b', etc. = the next Data In following DI b, etc. according to the programmed burst order Programmed Burst Length = 2, 4 or 8 in cases shown
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PRELIMINARY DATE: 9/8/00 .
W946432AD
Figure16:WRITE TO READ - DQSS, NON - INTERRUPTING
T0 CK CK COMMAND WRITE Bank, Col b NOP NOP NOP READ NOP WRITE TO READ - DQSS, NON - INTERRUPTING T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
tWTR
ADDRESS Bank, Col n
tDQSS
DQS DI b
CL=3
DQ
DM DON'T CARE
DI b, etc. = Data In for column b, etc. A non-interrupted burst of 4 is shown tWTR is referenced from the first postive CK edge after the last Data In pair A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled) The READ andWRITE commands may be to any bank, and may be to the same or different devices In the case where the READ and WRITE commands are to different devices, tWTR need not be met, and the READ command can be applied earlier tWTR = 2 tCK for optional CL = 1.5 (otherwise tWTR = 1 Tck)
Figure17:WRITE TO PRECHARGE - DQSS, NON - INTERRUPTING
T0 CK CK COMMAND WRITE Bank a, Col b NOP NOP NOP NOP PRE Bank (a or all) WRITE TO PRECHARGE - DQSS, NON-INTERRUPTING T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
tWTR
ADDRESS
tDQSS
DQS DI b
tRP
DQ
DM DON'T CARE
DI b, etc. = Data In for column b, etc. A non-interrupted burst of 4 is shown tWTR is referenced from the first postive CK edge after the last Data In pair A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
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PRELIMINARY DATE: 9/8/00 .
W946432AD
Figure18:WRITE TO PRECHARGE - DQSS, INTERRUPTING
T0 CK CK COMMAND WRITE Bank a, Col b NOP NOP NOP PRE Bank (a or all) NOP WRITE TO PRECHARGE - DQSS, INTERRUPTING T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
tWTR
ADDRESS
tDQSS
DQS DI b
*2
tRP
DQ
DM
*1
*1 DON'T CARE
DI b = Data In for column b A interrupted burst of 4 or 8 is shown, 2 data elements are written 1 subsequent element of Data In is applied in the programmed order following DI b tWTR is referenced from the first postive CK edge after the last desired Data In pair The PRECHARGE command masks the last two data elements in the burst A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled) *1 = can be don't care for programmed burst length of 4 *2 = for programmed burst length of 4, DQS becomes don't care at this point
Figure19:WRITE TO PRECHARGE - DQSS, ODD NUMBER OF DATA, INTERRUPTING
WRITE TO PRECHARGE - DQSS, ODD NUMBER OF DATA, INTERRUPTING T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK CK COMMAND WRITE Bank a, Col b NOP NOP NOP PRE Bank (a or all) NOP
tWTR
ADDRESS
tDQSS
DQS DI b
*2
tRP
DQ
DM
*1
*1 DON'T CARE
DI b = Data In for column b A interrupted burst of 4 or 8 is shown, 1 data element is written tWTR is referenced from the first postive CK edge after the last desired Data In pair The PRECHARGE command masks the last two data elements in the burst A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled) *1 = can be don't care for programmed burst length of 4 *2 = for programmed burst length of 4, DQS becomes don't care at this point
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PRELIMINARY DATE: 9/8/00 .
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Figure20:POWER - DOWN POWER - DOWN CK CK CKE
tIS
tIS
COMMAND
VALID No column access in progress
NOP
NOP
VALID
Enter power-down mode
Enter power-down mode DON'T CARE
Figure21:DATA INPUT (WRITE) TIMING
tDQSL tDQSH
DQS
DATA INPUT (WRITE) TIMING
tDS
DQ
tDH
DM
tDS
tDH
DON'T CARE
Dl n = Data In for column n Burst Length = 4 order following Dl n
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PRELIMINARY DATE: 9/8/00 .
W946432AD
Figure22:DATA OUTPUT (READ) TIMING
DATA OUTPUT (READ) TIMING
tDQSQ
tDQSQ
DQS max
nom
DQ
tDV
1.tDQSQ max occurs when DQS is earliest among DQS signals to transition. 2.tDQSQ min occurs when DQS is the latest among DQS and DQ signals to transition. 3.tDQSQ nom, shown for reference, occurs when DQS transitions in the center among DQ signal transitions. 4.Burst Length = 4
tDQSQ
min
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PRELIMINARY DATE: 9/8/00 .
W946432AD
Figure23:POWER - DOWN MODE
tCK
CK CK CKE
tCH tCL tIS
POWER- DOWN MODE
tIS tIH tIS tIH
tIS
COMMAND
VALID*
NOP
NOP
VALID
tIS tIH
ADDR VALID VALID
DQS
DQ
DM
Enter Power-Down Mode
Exit Power-Down Mode DON'T CARE
No column accresses are allowed to be in progress at the Power-Down is entered * = If this command is a PRECHARGE (or if the device is already in the idle state) then the Power-Down mode shown is Precharge Power Down. If this command is an ACTIVE (or if at least one row is already active) then the Power-Down mode shown is Active Power Down
30
W946432AD
Figure24:AUTO REFRESH MODE
tCK
CK CK CKE
tCH tCL
AUTO REFRESH MODE
tIS tIH tIS tIH
COMMAND
NOP
PRE
NOP
NOP
AR
NOP
AR
NOP
NOP
ACT
A0-A7
RA
A9,A10 ALL BANKS A8 ONE BANK BA0,BA1 *Bank(s)
RA
RA
BA
tIS tIH
DQS
DQ
DM
tRP
tRC
tRC
DON'T CARE
* = "Don't Care", if A8 is HIGH at this point; A8 must be HIGH if more than one bank is active (i.e. must precharge all active banks) PRE = PRECHARGE, ACT = ACTIVE, RA ROW Address, BA = BANK Address, AR = AUTOREFRESH NOP commands are shown for ease of illustration; other valid commands may be possible at these time DM, DQ and DQS signals are all "Do'nt Care"/High-z for operations shown
31
W946432AD
Figure25:SELF REFRESH MODE
tCH
CK CK CKE
SELF REFRESH MODE clock must be before tCL exiting Self Refresh Mode
tIS tIH tIS tIH
tIS
tCK
tIS tIS tIH
COMMAND
NOP
AR
NOP
VALID
ADDR
VALID
DQS
DQ
DM
tRP*
Enter Self Refresh Mode
tXSNR/ tSNR**
Exit Self Refresh Mode DON'T CARE
* = Device must be in tje "All banks idle" state prior to entering Self Refresh Mode ** = tXNR is required before any non-READ command can be applied, and tSNRD (200 cycles of CLK) are required befor READ command can be applied.
32
W946432AD
Figure26:READ - WITHOUT AUTO PRECHARGE
tCK
CK CK CKE
tCH tCL
READ-WITHOUT AUTO PRECHARGE
tIS tIH tIS tIH
COMMAND
NOP
READ
NOP
NOP
PRE
NOP
NOP
ACT
NOP
NOP
tIS tIH
A0-A7 Col n RA
A9,A10
RA
tIS tIH
A8 DIS AP
ALL BANKS RA ONE BANK *Bank x CL = 3 Bank x
tIS tIH
BA0,BA1 Bank x
tRP tDQSCK
min
DM
tAC/tDQSCK=min
DQS
tRPRE tLZ
min
tRPST tHZ
DQ
tLZ
min
DO n
min
tAC
min
tAC/tDQSCK=max
DQS
tRPRE
tDQSCK
max
tRPST tHZ
DQ
tLZ
max
DO n
max
tAC
max DON'T CARE
DO n = Data Out from column n Burst Length = 4 DIS AP = Disable Autoprecharge * = "Don't Care", if A8 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times
33
W946432AD
Figure27:READ - WITH AUTO PRECHARGE
tCK
CK CK CKE
tCH tCL
READ-WITH AUTO PRECHARGE
tIS tIH tIS tIH
COMMAND
NOP
READ
NOP
NOP
NOP
NOP
NOP
ACT
NOP
NOP
tIS tIH
A0-A7 Col n RA
A9,A10 EN AP A8
RA
RA
tIS tIH
BA0,BA1 Bank x CL = 3 DM Bank x
tRP tDQSCK
min
tAC/tDQSCK=min
DQS
tRPRE tLZ
min
tRPST tHZ
DQ
tLZ
min
DO n
min
tAC
min
tAC/tDQSCK=max
DQS
tRPRE
tDQSCK
max
tRPST tHZ
DQ
tLZ
max
DO n max
max
tAC
DON'T CARE
DO n = Data Out from column n Burst Length = 4 EN AP = Enable Autoprecharge ACT = ACTIVE, RA = Row Address NOP commands are shown for ease of illustration; other commands may be valid at these times
34
W946432AD
Figure28:BANK READ ACCESS
tCK
CK CK CKE
tCH tCL tIS tIH
BANK READ ACCESS
tIS tIH
COMMAND ACT NOP NOP NOP READ NOP NOP PRE NOP NOP ACT
A0-A7
RA
Col n
RA
A9,A10
RA
RA
tIS tIH
A8 RA
ALL BANKS RA ONE BANK *Bank x Bank x
tIS tIH
BA0,BA1 Bank x
DIS AP Bank x
tRC tRAS tRCD
DM CL=3
tRP
tAC/tDQSCK=min
DQS
tRPRE tLZ
min
tDQSCK
min
tRPST tHZ
DQ
tLZ
min
DO n
min
tAC
min
tAC/tDQSCK=max
DQS
tRPRE
tDQSCK
max
tRPST tHZ
DQ
tLZ
max
DO n max
max
tAC
DON'T CARE
DO n = Data Out from column n Burst Length = 4 DIS AP = Disable Autoprecharge * = "Don't Care", if A8 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Note that tRCD MIN so that the same timing applies if Autoprecharge is enabled (in which case tRAS would be limiting)
35
W946432AD
Figure29:WRITE - WITHOUT AUTO PRECHARGE
tCK
CK CK CKE
tCH tCL
WRITE - WITHOUT AUTO PRECHARGE
tIS tIH tIS tIH
tIH
COMMAND
NOP
WRITE
NOP
NOP
NOP
NOP
PRE
NOP
NOP
ACT
tIS tIH
A0-A7 Col n RA
A9,A10
RA
tIS tIH
A8
ALL BANKS RA ONE BANK *Bank x BA
tIS tIH
BA0,BA1 Bank x
DIS AP
tDQSS=min
DQS
tDSH tDQSS tDQSH tWPRES tWPRE
tDSH tWPST
tWR
tRP
tDQSL
DI n
DQ
DM
tDSS tDQSS=max
DQS
tDSS tWPST
tDQSS tWPRES tWPRE
tDQSH
tDQSL
DI n
DQ
DM DON'T CARE
DI n = Data IN from column n Burst Length = 4 DIS AP = Disable Autoprecharge * = "Don't Care", if A8 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times
36
W946432AD
Figure30:WRITE - WITH AUTO PRECHARGE
tCK
CK CK CKE
tCH tCL
WRITE - WITH AUTO PRECHARGE
tIS tIH tIS tIH
COMMAND
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ACT
tIS tIH
A0-A7 Col n RA
A9,A10 EN AP A8
RA
RA
tIS tIH
BA0,BA1 Bank x BA
tDQSS=min
DQS
tDSH tDQSS tDQSH tWPRES tWPRE
tDSH tWPST
tDAL
tDQSL
DI n
DQ
DM
tDSS tDQSS=max
DQS
tDSS tWPST
tDQSS tWPRES tWPRE
tDQSH
tDQSL
DI n
DQ
DM DON'T CARE
DI n = Data IN from column n Burst Length = 4 EN AP = Disable Autoprecharge ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times
37
W946432AD
Figure31:BANK WRITE ACCESS tCK
CK CK CKE
tCH tCL
BANK WRITE ACCESS
tIS tIH tIS tIH
COMMAND
NOP
ACT
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
PRE
tIS tIH
A0-A7 RA Col n
A9,A10
RA
tIS tIH
A8 RA DIS AP
ALL BANKS ONE BANK
tIS tIH
BA0,BA1 Bank x *Bank x
*Bank x
tRCD tDQSS=min
DQS
tRAS tDSH tDQSS tDQSH tWPRES tWPRE tDSH tWPST tWR
tDQSL
DI n
DQ
DM
tDSS tDQSS=max
DQS
tDQSS tWPRES tWPRE
tDQSH
tDSS tWPST
tDQSL
DI n
DQ
DM DON'T CARE
DI n = Data IN from column n Burst Length = 4 DIS AP = Disable Autoprecharge * = "Don't Care", if A8 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times
38
W946432AD
Figure32:WRITE - DM OPERATION tCK
CK CK CKE
tCH tCL
WRITE - DM OPERATION
tIS tIH tIS tIH
tIH
COMMAND
NOP
WRITE
NOP
NOP
NOP
NOP
PRE
NOP
NOP
ACT
tIS tIH
A0-A7 Col n RA
A9,A10
RA
tIS tIH
A8 DIS AP
ALL BANKS RA ONE BANK *Bank x BA
tIS tIH
BA0,BA1 Bank x
tDQSS=min
DQS
tDSH tDQSS tDQSH tWPRES tWPRE
tDSH tWPST
tWR
tRP
tDQSL
DI n
DQ
DM
tDSS tDQSS=max
DQS
tDSS tWPST
tDQSS tWPRES tWPRE
tDQSH
tDQSL
DI n
DQ
DM DON'T CARE
DI n = Data IN from column n Burst Length = 4 DIS AP = Disable Autoprecharge * = "Don't Care", if A8 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times
39
W946432AD
PACKAGE DIMENSIONS
H D D
E
H
E
e
b
c
A2 A See Detail F Seating Plane A1 y L L1
Controlling dimension : Millimeters
Symbol
Dimension in inch
Dimension in mm
Min Nom Max
0.002 0.004 0.053 0.055 0.009 0.013 0.004 0.006 0.547 0.551 0.783 0.787 0.020 0.026 0.626 0.862 0.018 0.630 0.866 0.024 0.039 0.003 0 7 0.006 0.057 0.015 0.008 0.555 0.791 0.032 0.634 0.870 0.030
Min Nom Max
0.05 1.35 0.22 0.10 13.90 19.90 0.10 1.40 0.32 0.15 0.15 1.45 0.38 0.20
A A1 A2 b c D E e HD HE L L1 y
14.00 14.10 20.00 20.10 0.802
0.498 0.65 15.90 21.90 0.45
16.00 16.10 22.00 22.10 0.60 1.00 0.08 0.75
0
7
40

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